1. Field of the Invention
This invention relates to a semiconductor memory device having memory cells each formed of a MOS transistor and a capacitor, and a manufacturing method for the semiconductor memory device.
2. Description of the related art including information disclosed under .sctn..sctn.1.97-1.99:
With recent MOS type DRAMs (Dynamic Random Access Memories) a great number of unit memory cells are integrated on a chip. Each unit memory cell is formed of a MOS transistor and a capacitor connected in series with the transistor. To increase the number of the unit memory cells to be integrated on a chip, it is desired that the area occupied by each memory cell be reduced. However, the reduction in the area occupied by the memory cell will lead to reduction in the capacitance of the capacitor, thus lowering the reliability of the DRAM. For this reason various structures of the unit memory cell have heretofore been developed in order to reduce the area occupied by the unit memory cell without decreasing the capacitance of the capacitor.
A typical example of such unit memory cell structures is shown in FIG. 1. This unit memory cell is well known as FCC (Folded Capacitor Cell) structure.
In FIG. 1, a groove 2 is formed in a semiconductor substrate 1. In a memory cell forming region 3 surrounded by groove 2, a MOS transistor is formed which has a source region, a drain region, a gate insulating layer 4, and a gate electrode 5. Groove 2 is comprised of a first region groove and a second region groove. In the first region groove are formed a first oxide layer 5 adapted for electrically isolating memory cell forming region 3, and a second oxide layer 6 adapted for forming a capacitor. Second oxide layer 6 is formed to cover a region 7 of an opposite conductivity type to substrate 1. Further, a capacitor electrode 8 is formed in the first region groove to contact second oxide layer 6. First oxide layer 5 also is formed in the second region groove as shown.
The above-mentioned structure of the unit memory cell has the following drawbacks.
Since first oxide layer 5 of the same thickness as the width of groove 2 is embedded in the lower portion of the first region groove and in the second region groove, crystal defects will be caused in substrate 1 by stress resulting from a difference between thermal expansion coefficients of substrate 1 and oxide layer 5. Further, during an etching process required to leave first oxide layer 5 in the bottom portion of the first region groove only, the width of the upper portion of the first region groove will broaden. It is difficult, therefore, to leave first oxide layer 5 in the lower portion of the first region groove.
The crystal defects increase junction leaks, and the broadening of the groove width decreases the capacitor area, thus degrading the performance of the DRAM.